Recently, with a larger data capacity, newly introduced broader band service represented by a video distribution, etc., a high-speed transmission is earnestly requested. As a technology to realize a high-speed transmission, a parallel transmission technology has attracted much attention. A multi-lane distribution (MLD) is one of the parallel transmission technologies.
In the MLD, a high-speed communication is realized using a plurality of lane as transmission lines. The data to be transmitted is divided into 66-bit blocks by a 64B-66B encoding process, and allocated to the respective lanes. When the number of the allocated blocks (physical coding sublayer (PCS) lanes) is larger than the number of lanes (physical lanes), a plurality of PCS lanes are bit-multiplexed for transmission on one physical lane.
In a parallel transmission using a plurality of physical lanes, askew (delay time difference) occurs between physical lanes in the data transmission. To solve the skew, a special marker specific to each PCS lane (alignment marker) is inserted for every 16,384 blocks in the MLD. On the data reception side, the alignment marker is detected for each PCS lane and the skew between the PCS lanes is corrected from the position of the detection.
The alignment marker is the information having a function of identifying a PCS lane. Inserted into each PCS lane is an alignment marker indicating the lane number as identification information assigned to the PCS lane. Thus, on the data reception side, the lane number indicated by the detected alignment marker is specified for each PCS lane, and the correct order of the block received by each PCS lane is reconstructed using the specified lane number.
A data reception device corresponding to an alignment marker has to detect an alignment marker for each PCS lane, and specify a lane number indicated by the detected alignment marker. The correspondence between the PCS lane and the physical lane may be changed. Furthermore, it is very hard to specify in advance with high accuracy the position into which the alignment marker has been inserted. Thus, the conventional data reception device detects an alignment marker and arranges a decoder for specification of a lane number for each type of alignment marker and for each phase in each PCS lane. In this specification, the phase corresponds to the part (range) in the received data which is an input of a decoder.
When data is input in a decoder in a range in which the data is bit-shifted, the number of ranges in which the data is input in the decoder is about 20. There are, for example, 20 types of alignment markers. Thus, if the number of PCS lanes is 20, the conventional data reception device are loaded with a total of 8000 (20×20×20) decoders.
When a number of decoders are loaded, the circuit scale of the data reception device and the power consumption are increased. Furthermore, the transmission path of data becomes long because data is input to a large number of decoders, thereby hardly performing a high-speed operation. Thus, it is important to minimize the number of decoders in the data reception device compatible with an alignment marker.
Some documents including Japanese Examined Patent Application Publication No. 06-28383, Japanese Patent No. 2955576, Japanese Laid-open Patent Publication No. 06-20391, etc are well known.